FPGA early input output planning

Hi Sameerr11,

First of all, the partnummer you mention is unknown. Probably a typo.

Making an early pin planning is not to difficult. I suppose you have Quartus II installed. Lets take a schematic as a toplevel.

- Open QII.

- select file > new > Quartus II project

- In the wizard, answer all the questions.

- When finished, select file > new > block diagram/schematic file

- Select the symbol tool at the left of the schematic (AND symbol)

- Unfold till you get pin: bidir, input, output

- Put the appropiate pins in the schematic

- Change names (address-bus could be A[18..0])

- Save under the same name as project name

- Start Analysis & Sythesis

- Ignore warnings about "missing source"

- When finished, go to assignments > pins

- Assign the pins.

- Redo Analysis & Sythesis

Finished. Just to give you a quick start.

I probably forgot some steps. Check the QII handbook for details.

Good luck, Ton