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TC,
Thanks for your answer.
Maybe it's a simple question, I don’t need a delay time data so accurately. Somebody measured the delay time by an oscilloscope, but my mine can’t do that for low frequency. I do need a small delay for hold-time.
-Limon
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Its a simple question, with an answer that wont be acceptable to you.
Using gates and logic for delays is just pure bad practice. Apart from the PVT variations, unless you lock down the placement and the routing this will also have a big effect on timing too.
So the main answer is DONT DO IT!
You should be using the IO timing delay blocks, and providing timing specs in your .sdc file.
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