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Altera_Forum
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17 years ago

FPGA Configuration with JTAG

Hey All, I have an interesting issue. I have a EP2C35F484 FPGA mounted on a FireflyII board (adds some memory, an oscillator, serial configuration chip and max232 converter). I am able to loa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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The output pin was a valid pin. I used the same output pin in the NIOS application wihtout any problem.

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It doesn't make sense to say your vhdl doesn't work while nios works(nios is just vhdl platform produced by SOPC).

I am sure your testing is wrong, try signaltap instead of pins and make sure your vhdl is not optimised away.