FPGA configuration time and PCIe secification

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Has anyone used the PCIe interface of a Cyclone device while configuring it using the AS (active serial) scheme?

I'm using a Cyclone IV device (EP4CGX30F484) and planning to use its PCIe interface. I've read from the PCIe specification that the minimum time between the PC's power rails being stable and the PCIe PERST# signal being deactivated is T_PVPERL = 100 ms (acitvating and deactivating PERST# causes a reset of the PCIe interface and causes PCIe lanes to initialise). You get another 100 ms from receiving the PERST# signal before the sequence starts, so that's a total of 200 ms. The PCIe specification only states a minimum time between power being stable and sending the PERST# signal, so you could get a few seconds before you have to be ready, but I don't know if I can rely on this.

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You actually need to read several specifications to track down the timing parameters. I've attached a few pages from a document that cross-references the information you're interested in.

Unfortunately the answer to the question "How soon does the PCIe end-point need to be ready?" doesn't really have a simple answer, since it depends on your application. In the CPCI-S.0 application I'm working on, the PCIe end-point just has to be ready before the host processor deasserts PCIe RST#, and from hardware measurements on the CPUs I intend to use, it appears I have 800ms. This is lucky for me, as the peripheral board needs to use a hot-swap controller, and hot-swap controller all seem to have power-on delays of 100ms!

The power-on timing is harder for PCIe motherboard applications, as there you really have no control over the motherboard reset timing, so you need to be ultra-conservative and meet the TPVPERL = 100ms specification.

Cheers,

Dave

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1). So, how much time is available for configuration: 100 ms or 200ms?

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The design target for a product should be under 100ms. If you are designing the board for your own system, and you have a specific host CPU or motherboard you are planning to use, then measure the PCI RST# time on the motherboard and design based on that.

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2). How to calculate the total configuration time?

POR can be taken from CIV datasheet and it is 3ms for Fast POR

What other time should be taken into account to calculate the total configuration time and where in CIV datasheet is it specified?

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The total configuration timing sequence is;

1) External power gets turned on to the "system"; motherboard or chassis, main host CPU, and PCIe bridges and devices.

2) The power supplies for the host and the peripheral devices start ramping up.

The timing for this part is completely arbitrary and depends on the system design.

In the case of your FPGA-based PCIe end-point, you'll have whatever ramp time your power supplies require, and if you've specified a fast POR, they need to ramp within that time.

3) Once the power supplies are in spec, the FPGA configures, eg., via Active Serial, Passive Serial, or Fast Passive Parallel.

4) The BIOS or host CPU bootloader enumerates the PCIe bus.

So long as (3) completes before (4), your system will work, otherwise it will not, as the PCIe device will not be enumerated.

Cheers,

Dave

The Answer - I havent used a cyclone for it, but we did use a stratix 2 GX in this scheme. The result - some boards that wont boot in some motherboards - and it wasnt even a specific manufacturer thing - some boards worked and some didnt.

The larger devices take a long time to program, so will fall outside the PCIe spec. You HAVE to use FPP or you're going to have problems. But Max IIs can do it and are very cheap and very small. The PCIe dev boards all use the FPP scheme if you need a reference design. Theres even a free FPP block you can pull out of the megawizard, so design is pretty small.

Hi

It wasnt my project but I know there were problems. IIRC, the config time was fairly close to the spec, 200ms, hence it working most of the time.

If you're not up in time, a PC or similar is never going to see the board.

thought i'd throw out another alternative: Cyclone V and autonomous HIP. this configures the FPGA via AS in 2 stages, the periphery and the core. loading the periphery first allows you to meet PCIe specs, then the FPGA goes out and reads the core image:

http://www.altera.com/literature/ug/ug_cvp.pdf

The 'split config' doesn't work in any available Cyclone IV devices.

IIRC It is supposed to be functional in the rev C part - not yet available.

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The 'split config' doesn't work in any available Cyclone IV devices.

IIRC It is supposed to be functional in the rev C part - not yet available.

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In what Altera document can I find more information about it?