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Has anyone used the PCIe interface of a Cyclone device while configuring it using the AS (active serial) scheme?
I'm using a Cyclone IV device (EP4CGX30F484) and planning to use its PCIe interface. I've read from the PCIe specification that the minimum time between the PC's power rails being stable and the PCIe PERST# signal being deactivated is T_PVPERL = 100 ms (acitvating and deactivating PERST# causes a reset of the PCIe interface and causes PCIe lanes to initialise). You get another 100 ms from receiving the PERST# signal before the sequence starts, so that's a total of 200 ms. The PCIe specification only states a minimum time between power being stable and sending the PERST# signal, so you could get a few seconds before you have to be ready, but I don't know if I can rely on this.
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You actually need to read several specifications to track down the timing parameters. I've attached a few pages from a document that cross-references the information you're interested in.
Unfortunately the answer to the question "How soon does the PCIe end-point need to be ready?" doesn't really have a simple answer, since it depends on your application. In the CPCI-S.0 application I'm working on, the PCIe end-point just has to be ready before the host processor deasserts PCIe RST#, and from hardware measurements on the CPUs I intend to use, it appears I have 800ms. This is lucky for me, as the peripheral board needs to use a hot-swap controller, and hot-swap controller all seem to have power-on delays of 100ms!
The power-on timing is harder for PCIe motherboard applications, as there you really have no control over the motherboard reset timing, so you need to be ultra-conservative and meet the TPVPERL = 100ms specification.
Cheers,
Dave
Honored Contributor
