--- Quote Start ---
1). So, how much time is available for configuration: 100 ms or 200ms?
--- Quote End ---
The design target for a product should be under 100ms. If you are designing the board for your own system, and you have a specific host CPU or motherboard you are planning to use, then measure the PCI RST# time on the motherboard and design based on that.
--- Quote Start ---
2). How to calculate the total configuration time?
POR can be taken from CIV datasheet and it is 3ms for Fast POR
What other time should be taken into account to calculate the total configuration time and where in CIV datasheet is it specified?
--- Quote End ---
The total configuration timing sequence is;
1) External power gets turned on to the "system"; motherboard or chassis, main host CPU, and PCIe bridges and devices.
2) The power supplies for the host and the peripheral devices start ramping up.
The timing for this part is completely arbitrary and depends on the system design.
In the case of your FPGA-based PCIe end-point, you'll have whatever ramp time your power supplies require, and if you've specified a fast POR, they need to ramp within that time.
3) Once the power supplies are in spec, the FPGA configures, eg., via Active Serial, Passive Serial, or Fast Passive Parallel.
4) The BIOS or host CPU bootloader enumerates the PCIe bus.
So long as (3) completes before (4), your system will work, otherwise it will not, as the PCIe device will not be enumerated.
Cheers,
Dave
Honored Contributor
