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Altera_Forum's avatar
Altera_Forum
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11 years ago

FPGA can't properly work at my input CLK.

In my design,I found the clock can not properly work. The input clock is 66Mhz, if this signal directly is connected to the output pin, the output will get a signal of 66MHz. That's ok. but!!!...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I'm no expert at PLL's but if it gives you 132 mhz, why not just divide it by 2 :-)

-Mux