Force a signal in the output of a logical gate: destructive?

I've got an other question.

I've got an error: Pin "name" is stuck at GND. In my design, and in normal operation, this pin will be all the time at GND. But If there is a SEU at a bad place, there is a possibility it goes high, so it is usefull (because the purpose of this pin is to detect the SEU...)

My question is: is the program implement exactly the schematics, or does it detect this "error", and the do some optimization?

I've got an other warning just after saying that this pin does not drive any logic, so I'm a bit afraid that the system removed for optimization purpose this part of my design...

If yes, is it possible to force it to implement my design exactly? (I'm currently using the schematic editor to implement my design...)