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Altera_Forum
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14 years ago

Force a signal in the output of a logical gate: destructive?

Hi all! I've got a question that seems rather stupid at first: what happens if I try to put a signal in the output of a FPGA logic? Let me explain why this problem could happen: I have to ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thank you very much for your help.

I'll have some reading for the next days then :p

I know it's not a good idea to have a port in the wrong direction, but the problem is that I can't have control over SEU (single event upset caused by charged particle in space). In the meanwhile, I've minimized as much as possible the weak spot of my design (I mean the place where a SEU can operate and the cause an electrical conflict).

Again, thanks a lot :)