Hi, I hope this makes sense, I can explain it if not. Thanks again
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/* dividing time*/
if(en_divi)
begin
fcnt7<=fcnt7+1;
if (fcnt7>4) // waS 4
begin
if(Add3>=MxN-1)
begin
memBD_f32[Add3]<=div1_f32;
Add3<=0;
en_divi<=0;
en_divi2<=1;
end
else
begin
memBD_f32[Add3]<=div1_f32;
Add3<=Add3+1;
end
end
end //end of en_divi
if(en_divi2)
begin
d2_en<=1;
if(Add3>=MxN-1)
begin
tempA2<=memA_f32[Add3];
tempX<=memX_f32 [Add3];
Add3<=0;
end
else
begin
tempA2<=memA_f32[Add3];
tempX<=memX_f32 [Add3];
Add3<=Add3+1;
fcnt8<=fcnt8+1;
end
if (fcnt8>5) // output latency is 6
begin
if(Add4>=MxN-1)
begin
memTD_f32[Add4]<=div2_f32;
Add4<=0;
en_divi2<=0;
d2_en<=0;
end
else
begin
memTD_f32[Add4]<=div2_f32;
Add4<=Add4+1;
end
end
end //end of en_divi2
divi_f32 divi_bmexp(reset,en_divi,CLK,max_f32,Xop_f32,div1_f32); //bottom
divi_f32 divi_tmexp(reset,d2_en,CLK,tempX,tempA2,div2_f32); // top divide
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