Forum Discussion
Honored ContributorFloating point megafunctions
Hello,
Has anyone had a problem with the altera's mega functions? My 1st output when I used the divide is always 3fdfffc0. And I always enable as soon as I store my 1st input. Also, just to confirm 'dataa' <= is the numerator13 Replies
Altera_ForumLooks like it is setup correctly. Perhaps you are running into this (but I doubt it since I think the simulation would fail to compile): http://www.alteraforum.com/forum/showthread.php?t=22653
I recommend opening a service request on this one: http://www.altera.com/mysupport- Altera_Forum
Hello,
Sorry for the late reply. Attached here - Altera_Forum
Ok I guess you used the megawizard GUI to output the HDL. Do you have an instantiation file that shows how divider was parameterized? You'll probably find it in whatever file contains the "divi_f32" module.
- Altera_Forum
Hello,
--- Quote Start --- divi_f32 divi_bmexp(reset,en_divi,CLK,max_f32,Xop_f32,div1_ f32);//bottom divi_f32 divi_tmexp(reset,d2_en,CLK,tempX,tempA2,div2_f32); // top divide --- Quote End --- I added the other part to show when I start storing the values - Altera_Forum
I mean the instantiation of altfp_div not the logic around it.
- Altera_Forum
Hi, I hope this makes sense, I can explain it if not. Thanks again
*********************************************************** /* dividing time*/ if(en_divi) begin fcnt7<=fcnt7+1; if (fcnt7>4) // waS 4 begin if(Add3>=MxN-1) begin memBD_f32[Add3]<=div1_f32; Add3<=0; en_divi<=0; en_divi2<=1; end else begin memBD_f32[Add3]<=div1_f32; Add3<=Add3+1; end end end //end of en_divi if(en_divi2) begin d2_en<=1; if(Add3>=MxN-1) begin tempA2<=memA_f32[Add3]; tempX<=memX_f32 [Add3]; Add3<=0; end else begin tempA2<=memA_f32[Add3]; tempX<=memX_f32 [Add3]; Add3<=Add3+1; fcnt8<=fcnt8+1; end if (fcnt8>5) // output latency is 6 begin if(Add4>=MxN-1) begin memTD_f32[Add4]<=div2_f32; Add4<=0; en_divi2<=0; d2_en<=0; end else begin memTD_f32[Add4]<=div2_f32; Add4<=Add4+1; end end end //end of en_divi2 divi_f32 divi_bmexp(reset,en_divi,CLK,max_f32,Xop_f32,div1_f32); //bottom divi_f32 divi_tmexp(reset,d2_en,CLK,tempX,tempA2,div2_f32); // top divide ****************************************************** - Altera_Forum
That is odd, I would have expected 0x42c20000 / 0x42994000 = 0x3fa20930. Copy and paste you instantiation of the divider into this post, maybe there is something incorrectly set.
- Altera_Forum
Hello,
Attached is a snapshot of my simulation. I think the enable is fine because datab comes in at the same time as the enable=1 - Altera_Forum
Are you simulating this design? If not then I would recommend doing so just in case the enable bit is not timed correctly.
- Altera_Forum
Thank you for the quick reply,
But my answers do not match. I had y= a/b a= 81 b= 76.6 Y= 1.057 but my answer is always 3fdfffc0 at the 1st output (which is 1.74999237060546875e0 ) I dont know what I am doing wrong. I wait for 6clock cycles before I store my values
