Altera_ForumHonored Contributor14 years agoFloating point megafunctions Hello, Has anyone had a problem with the altera's mega functions? My 1st output when I used the divide is always 3fdfffc0. And I always enable as soon as I store my 1st input. Al...Show More
Altera_ForumHonored Contributor14 years agoI mean the instantiation of altfp_div not the logic around it.
Recent DiscussionsCyclone V SoC 5CSXC6 Series GXB Utilization and LimitationsHow to tell Quartus my Arria10 target system CLKUSR frequency is 100MHz?Agilex 3 PLL in Source Synchronous mode ?writing a word to cfm1 using on chip flash ip on max10MAX10 FPGA IOs not entering Tri-state (Hi-Z)