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Altera_Forum's avatar
Altera_Forum
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16 years ago

Flex 6000 clock gating

Hi I've been converting a 10 year old non-synchronous design to make synchronous so that it is more robust. Due to the available clocks on the board, it is necessary to use a gated clock. The o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Quite curious indeed.

I'd go and look at the postfitting netlist for -1 and -2 speed grades.

I'd also go and take a look at the waveforms for the pins of the LEs involved.

From there, you might be able to work arround the issue by placing a delay LCELL somewhere in the design.