flancter and timequest

Dear All,

i'm using classical implementation of flancter to realize signalling between multiple clock domains (see down).

Now, this design is proven to be hazard free, however timequest of course realizes, that e.g. SetFlopxS is driven by both clock domains. Is it OK to set the false path to this in the timequest?

thanks

d.

--! @brief implementation of flancter as shown in app note by B. Weinstein

entity flancter is

port (

ResetxRNA : in std_logic; --! reset signal

ClkSetxC : in std_logic; --! clock for setting signal domain

SetxS : in std_logic; --! set signal in ClkSetxC domain

ClkResetxC : in std_logic; --! clock for resetting signal domain

ResetxS : in std_logic; --! reset signal in ClkResetxC clock domain

QxM : out std_logic); --! output data

end flancter;

--! @brief implementation of flancter

architecture flancter of flancter is

signal SetFlopxS : std_logic;--! setting flop signal

signal RstFlopxS : std_logic;--! resetting flop signal

begin

set_proc : process(ResetxRNA, ClkSetxC)

begin

if ResetxRNA = '0' then

SetFlopxS <= '0';

elsif rising_edge(ClkSetxC) then

if SetxS = '1' then

SetFlopxS <= not RstFlopxS;

end if;

end if;

end process;

reset_proc : process(ResetxRNA, ClkResetxC)

begin

if ResetxRNA = '0' then

RstFlopxS <= '0';

elsif rising_edge(ClkResetxC) then

if ResetxS = '1' then

RstFlopxS <= SetFlopxS;

end if;

end if;

end process;

QxM <= SetFlopxS xor RstFlopxS;

end flancter;