flancter and timequest

Hi Dave,

sorry for late response.

In fact, I'm not trying to synchronize events, but rather generate a signal which is set in one domain, and reset in another domain. The application I have is, that I have to reset an external circuit, which is driven in different clock domain than FPGA. However the reset must asserted for an unknown time, for as long as another (input) signal from the circuit tells me, that reset was performed.

So I though that by using flancter I can set up the reset signal in my domain (120MHz), and when chip announces in its 40MHz clock domain that it finished, I use this signal in flancter to 'null' the reset signal.

I know that this could be probably realized by using two-ff at the input of the chip and resync this 40MHz signal into 120MHz and doing edge detection. But I thought that those two methods could be identical in what I need to do and save some registers. (I have plenty of them so no really need do to some economy here :)

I did not know however, that you need to use two-stage syncing as well for the signal coming from external chip. This information I got from the doulos link you sent earlier.

d.