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Altera_Forum
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14 years ago

flancter and timequest

Dear All, i'm using classical implementation of flancter to realize signalling between multiple clock domains (see down). Now, this design is proven to be hazard free, however timequest of cours...
Altera_Forum's avatar
Altera_Forum
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14 years ago

dejfson,

I agree with Dave.

- Assuming your signal comming from the 40 MHz domain is assured to last at least one 120 MHz cycle, using a cascade of DFF is, by far, the correct option.

- If not, using the toggle scheme and then the DFF cascade.

Regarding constrains,

Let's say r1 operate with clk1, and r2 and r3 operate with clk2.

set_false_path -from [get_pins r1|q]

set_false_path -to [get_pins r2|d]

...

In your case, since it's external

set_false_path -from [get_ports your_pin]