fixed delay chain & periphery clock

Hi,

I am trying to implement a fixed delay on CLK path.

Basically the CLK is DDR DQS to my DUT.

I have used LCELL logic to implement the delay I require but this delay is changing with each PAR run.

I need some logic somewhat like a Regional Buffer of Xilinx (we used this successfully for above experiment)

Regional Buffer -- Delay -- Regional Buffer

So the delay is fixed and always lies between the Buffers only.

Can someone guide me on How & What should i follow on Altera Devices (We are using Stratix-4)

Thanks