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Honored Contributor
Honored Contributorfixed delay chain & periphery clock
Hi, I am trying to implement a fixed delay on CLK path. Basically the CLK is DDR DQS to my DUT. I have used LCELL logic to implement the delay I require but this delay is changing with e...
Altera_ForumHonored Contributor
Honored ContributorWon't using the DQS pins and ALTDQS function be better?
If that doesn't work out, you can try to fix the LCELL's placement. But even so, it's subject to PVT variations.
