First verilog program problems.

Hey

I am working on my first verilog program, Basically it is a clock divider which divides the main clock 25mhz down to create a new slower clock this part is working ok. But I am trying to delay another pulse off the second clock and all I get it the output going low and nothing happens. I will post the code below if someone could tell me where I went wrong it would be great.

    module Detector(clk,clk_out,clk_second);
    input clk ;
    output reg clk_out;
    output reg clk_second;
    reg  counter;
    reg  counter1;
    
   
    always @(posedge clk) 
    begin
    if (counter==16'd0)
    begin
    clk_out <= ~clk_out;
    end
    if (counter==16'd750)
    begin
    clk_out <= ~clk_out;
    end  
    if(counter==16'd6500)
    begin
    counter<=16'd0;
    end
    else
    begin
    counter<=counter+1;
    end
    end
    
    always @ (posedge clk_out)
    begin 
    if (counter1==16'd1000)
    begin
    clk_second <= ~clk_second;
    end  
    else if (counter1==16'd1250)
    begin
    clk_second <= ~clk_second;
    counter1<=16'd0;
    end  
    else
    begin
    counter1<=counter1+1;
    end
    end 
    endmodule