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Altera_Forum's avatar
Altera_Forum
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15 years ago

First verilog program problems.

Hey I am working on my first verilog program, Basically it is a clock divider which divides the main clock 25mhz down to create a new slower clock this part is working ok. But I am trying t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for your replay, I cant believe I missed that I added

counter1<=counter1+1;

in the "if 1000" loop and now it works as expected. Thanks Again