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Honored Contributor
Honored ContributorFirst verilog program problems.
Hey I am working on my first verilog program, Basically it is a clock divider which divides the main clock 25mhz down to create a new slower clock this part is working ok. But I am trying t...
Altera_ForumHonored Contributor
Honored ContributorIn the second always block, counter1 is not changed when it equals 16'd1000, so it just counts to 1000 and stops.
