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Altera_Forum
Honored Contributor
13 years agoTricky, your amazing. Thanks heaps mate. I think my design should be alright as the buffer is reversed at the upper address limit and the pointers should never go over but I'll double check.
I do have one question though from reading the ram guidelines. Because it is being inferred as ram should I be expecting a delay in the output by a clock cycle and if so will this delay be imposed on the output of dval and fval as I need the outputs to be in sync. I got the impression from the guidelines that there will be a delay. Mat.