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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FlipBuffer is
generic(
LABEL_WIDTH : integer := 8;
COORD_WIDTH : integer := 10;
BUFFER_SIZE : integer := 765 -- Screen width
);
port(
-- Clock Signal
CLK : in std_logic;
-- Input Signals
CL_IN : in unsigned(LABEL_WIDTH-1 downto 0);
X_IN : in unsigned(COORD_WIDTH-1 downto 0);
Y_IN : in unsigned(COORD_WIDTH-1 downto 0);
DVAL_IN : in std_logic := '0';
FVAL_IN : in std_logic := '0';
-- Output Signals
--VALID : out std_logic;
CL_OUT : out unsigned(LABEL_WIDTH-1 downto 0) := to_unsigned(0,LABEL_WIDTH);
X_OUT : out unsigned(COORD_WIDTH-1 downto 0) := to_unsigned(0,COORD_WIDTH);
Y_OUT : out unsigned(COORD_WIDTH-1 downto 0) := to_unsigned(0,COORD_WIDTH);
DVAL_OUT : out std_logic := '0';
FVAL_OUT : out std_logic := '0'
);
end FlipBuffer;
architecture rt1 of FlipBuffer is
-- output registers
signal cl_reg : unsigned(LABEL_WIDTH-1 downto 0);
signal x_reg : unsigned(COORD_WIDTH-1 downto 0);
signal y_reg : unsigned(COORD_WIDTH-1 downto 0);
signal dval_reg : std_logic := '0';
signal fval_reg : std_logic := '0';
-- Buffer
type FILO_CL_Stack is array(0 to BUFFER_SIZE-1) of unsigned(LABEL_WIDTH-1 downto 0);
type FILO_COORD_Stack is array(0 to BUFFER_SIZE-1) of unsigned(COORD_WIDTH-1 downto 0);
signal CL_Stack : FILO_CL_Stack;
signal X_Stack : FILO_COORD_Stack;
signal Y_Stack : FILO_COORD_Stack;
signal read : integer;
signal write : integer;
signal reverse : std_logic;
signal read_count : integer;
signal write_count : integer;
begin
process (CLK)
begin
if (rising_edge(CLK)) then
if (DVAL_IN = '0' and FVAL_IN = '0') then
-- reset, this will ignore the final line of the frame to ensure
-- initial conditions are set when the frame starts. However, the
-- final line is black and therefore makes no difference.
reverse <= '0';
read <= BUFFER_SIZE-1;
write <= 0;
read_count <= 0;
write_count <= 0;
cl_reg <= to_unsigned(0,LABEL_WIDTH);
x_reg <= to_unsigned(0,COORD_WIDTH);
y_reg <= to_unsigned(0,COORD_WIDTH);
dval_reg <= '0';
fval_reg <= '0';
elsif (DVAL_IN = '1' and FVAL_IN = '1' and read_count > 0) then
-- Reading and Writing state
-- Read first so data is not overwritten
cl_reg <= CL_Stack(read);
x_reg <= X_Stack(read);
y_reg <= Y_Stack(read);
dval_reg <= '1';
fval_reg <= '1';
-- Write data
CL_Stack(write) <= CL_IN;
X_Stack(write) <= X_IN;
Y_Stack(write) <= Y_IN;
-- Update counts and addresses
if (write_count + 1 = BUFFER_SIZE) then
-- Row writen, reverse buffer and start reading
reverse <= not reverse;
write <= write;
read <= write;
write_count <= 0;
read_count <= BUFFER_SIZE;
else
-- Still writing row
reverse <= reverse;
write_count <= write_count + 1;
read_count <= read_count + 1;
if (reverse = '0') then
write <= write + 1;
read <= read + 1;
else
write <= write - 1;
read <= read - 1;
end if;
end if;
elsif (DVAL_IN = '1' and FVAL_IN = '1' and read_count <= 0) then
-- Writing, NOT Reading state
-- NOT Reading
cl_reg <= to_unsigned(0,LABEL_WIDTH);
x_reg <= to_unsigned(0,COORD_WIDTH);
y_reg <= to_unsigned(0,COORD_WIDTH);
dval_reg <= '0';
fval_reg <= '1';
-- Write data
CL_Stack(write) <= CL_IN;
X_Stack(write) <= X_IN;
Y_Stack(write) <= Y_IN;
-- Update counts and addresses
if (write_count + 1 = BUFFER_SIZE) then
-- Row writen, reverse buffer and start reading
reverse <= not reverse;
write <= write;
read <= write;
write_count <= 0;
read_count <= BUFFER_SIZE;
else
-- Still writing row
reverse <= reverse;
write_count <= write_count + 1;
if (reverse = '0') then
write <= write + 1;
else
write <= write - 1;
end if;
read_count <= 0;
read <= 0;
end if;
elsif (DVAL_IN = '0' and FVAL_IN = '0' and read_count > 0) then
-- Reading, NOT Writing state
-- NOT Writing
reverse <= reverse;
write <= write;
write_count <= write_count;
-- Read data
cl_reg <= CL_Stack(read);
x_reg <= X_Stack(read);
y_reg <= Y_Stack(read);
dval_reg <= '1';
fval_reg <= '1';
-- Update counts and addresses
read_count <= read_count + 1;
if (reverse = '0') then
read <= read + 1;
else
read <= read - 1;
end if;
else
-- DO NOTHING, maintain state
reverse <= reverse;
read_count <= read_count;
write_count <= write_count;
read <= read;
write <= write;
cl_reg <= to_unsigned(0,LABEL_WIDTH);
x_reg <= to_unsigned(0,COORD_WIDTH);
y_reg <= to_unsigned(0,COORD_WIDTH);
dval_reg <= '0';
fval_reg <= '1';
end if;
end if;
end process;
CL_OUT <= cl_reg;
X_OUT <= x_reg;
Y_OUT <= y_reg;
DVAL_OUT <= dval_reg;
FVAL_OUT <= fval_reg;
end rt1;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Flip_test is
generic (
LABEL_WIDTH : integer := 8;
COORD_WIDTH : integer := 10;
BUFFER_SIZE : integer := 5--765 -- Screen width
);
end Flip_test;
architecture bench of Flip_test is
component FlipBuffer
port (
-- Clock Signal
CLK : in std_logic;
-- Input Signals
CL_IN : in unsigned(LABEL_WIDTH-1 downto 0);
X_IN : in unsigned(COORD_WIDTH-1 downto 0);
Y_IN : in unsigned(COORD_WIDTH-1 downto 0);
DVAL_IN : in std_logic := '0';
FVAL_IN : in std_logic := '0';
-- Output Signals
CL_OUT : out unsigned(LABEL_WIDTH-1 downto 0) := to_unsigned(0,LABEL_WIDTH);
X_OUT : out unsigned(COORD_WIDTH-1 downto 0) := to_unsigned(0,COORD_WIDTH);
Y_OUT : out unsigned(COORD_WIDTH-1 downto 0) := to_unsigned(0,COORD_WIDTH);
DVAL_OUT : out std_logic := '0';
FVAL_OUT : out std_logic := '0'
);
end component;
signal CLK, DVAL_IN, FVAL_IN, DVAL_OUT, FVAL_OUT : std_logic;
signal CL_IN, CL_OUT : unsigned(LABEL_WIDTH-1 downto 0);
signal X_IN, Y_IN, X_OUT, Y_OUT : unsigned(COORD_WIDTH-1 downto 0);
BEGIN
clk_process :process
begin
CLK <= '0';
wait for 100 PS;
CLK <= '1';
wait for 100 PS;
end process;
stim_process :process
variable odd : std_logic := '1';
variable run : std_logic := '1';
variable count : unsigned(COORD_WIDTH-1 downto 0) := to_unsigned(0,COORD_WIDTH);
begin
DVAL_IN <= '0';
FVAL_IN <= '0';
CL_IN <= to_unsigned(0, LABEL_WIDTH);
X_IN <= to_unsigned(0, COORD_WIDTH);
Y_IN <= to_unsigned(0, COORD_WIDTH);
wait for 150 ps;
DVAL_IN <= '0';
FVAL_IN <= '0';
CL_IN <= to_unsigned(4, LABEL_WIDTH);
X_IN <= to_unsigned(2, COORD_WIDTH);
Y_IN <= to_unsigned(3, COORD_WIDTH);
wait for 200 ps;
while (run = '1') loop
if (count = to_unsigned(20,COORD_WIDTH)) then
run := '0';
end if;
if (odd = '1') then
odd := '0';
DVAL_IN <= '1';
FVAL_IN <= '1';
count := count + 1;
CL_IN <= to_unsigned(8, LABEL_WIDTH);
X_IN <= count;
Y_IN <= count;
wait for 200 ps;
else
odd := '1';
DVAL_IN <= '0';
FVAL_IN <= '1';
--count := count + 1;
CL_IN <= to_unsigned(0, LABEL_WIDTH);
X_IN <= to_unsigned(333, COORD_WIDTH);
Y_IN <= to_unsigned(333, COORD_WIDTH);
wait for 200 ps;
end if;
end loop;
DVAL_IN <= '0';
FVAL_IN <= '0';
CL_IN <= to_unsigned(8, LABEL_WIDTH);
X_IN <= to_unsigned(222, COORD_WIDTH);
Y_IN <= to_unsigned(222, COORD_WIDTH);
run := '1';
wait for 200 ps;
while (run = '1') loop
if (odd = '1') then
odd := '0';
DVAL_IN <= '1';
FVAL_IN <= '1';
count := count + 1;
CL_IN <= to_unsigned(8, LABEL_WIDTH);
X_IN <= count;
Y_IN <= count;
wait for 200 ps;
else
odd := '1';
DVAL_IN <= '0';
FVAL_IN <= '1';
--count := count + 1;
CL_IN <= to_unsigned(0, LABEL_WIDTH);
X_IN <= to_unsigned(333, COORD_WIDTH);
Y_IN <= to_unsigned(333, COORD_WIDTH);
wait for 200 ps;
end if;
end loop;
--wait;
end process;
M: FlipBuffer port map (CLK, CL_IN, X_IN, Y_IN, DVAL_IN, FVAL_IN, CL_OUT, X_OUT, Y_OUT, DVAL_OUT, FVAL_OUT);
end bench;
