First in Last out buffer consuming too much resources

Thanks tricky,

I have written a testbench and fully tested the block, I just left it out of the post

so the post was not too long but I've included it below now.

With regards to the variables, there's no reason I need them in this design, my

previous design was simplified by using variables instead of signals and I just

didn't get around to changing them back to signals when I redesigned the block

but I will change them back to signals. What is the reason I should stick to

variables for now?

I will read the design guidelines for altera RAM, but my main question is,

is the fact that the arrays are not being inferred to RAM the reason why the

block is using so many logic elements?

Mat.

Testbench

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Flip_test is
  generic (
    LABEL_WIDTH	:	integer	:=	8;
		COORD_WIDTH	:	integer	:=	10;
		BUFFER_SIZE	:	integer	:=	5--765	-- Screen width
  );
end Flip_test;
architecture bench of Flip_test is
  component FlipBuffer
    port (
        -- Clock Signal
		    CLK			:	in	std_logic;
		
		    -- Input Signals
		    CL_IN			:	in	unsigned(LABEL_WIDTH-1 downto 0);
		    X_IN			 :	in unsigned(COORD_WIDTH-1 downto 0);
		    Y_IN			 :	in	unsigned(COORD_WIDTH-1 downto 0);
		    DVAL_IN :	in std_logic := '0';
		    FVAL_IN : in std_logic := '0';
		
		    -- Output Signals
		    CL_OUT		  :	out unsigned(LABEL_WIDTH-1 downto 0) := to_unsigned(0,LABEL_WIDTH);
		    X_OUT			  :	out unsigned(COORD_WIDTH-1 downto 0) := to_unsigned(0,COORD_WIDTH);
		    Y_OUT			  :	out unsigned(COORD_WIDTH-1 downto 0) := to_unsigned(0,COORD_WIDTH);
		    DVAL_OUT  :	out std_logic := '0';
		    FVAL_OUT  : out std_logic := '0'
    );
  end component;
  
  signal CLK, DVAL_IN, FVAL_IN, DVAL_OUT, FVAL_OUT  : std_logic;
  signal CL_IN, CL_OUT                : unsigned(LABEL_WIDTH-1 downto 0);
  signal X_IN, Y_IN, X_OUT, Y_OUT     : unsigned(COORD_WIDTH-1 downto 0);
  
BEGIN
  
  clk_process :process
  begin
    CLK <= '0';
    wait for 100 PS;
    CLK <= '1';
    wait for 100 PS;    
  end process;
  
  stim_process :process
    variable odd    : std_logic := '1';
    variable run    : std_logic := '1';
    variable count  : unsigned(COORD_WIDTH-1 downto 0) := to_unsigned(0,COORD_WIDTH);
  begin
    DVAL_IN <= '0';
    FVAL_IN <= '0';
    CL_IN <= to_unsigned(0, LABEL_WIDTH);
    X_IN <= to_unsigned(0, COORD_WIDTH);
    Y_IN <= to_unsigned(0, COORD_WIDTH);
    wait for 150 ps;
    DVAL_IN <= '0';
    FVAL_IN <= '0';
    CL_IN <= to_unsigned(4, LABEL_WIDTH);
    X_IN <= to_unsigned(2, COORD_WIDTH);
    Y_IN <= to_unsigned(3, COORD_WIDTH);
    wait for 200 ps;
    
    while (run = '1') loop
      if (count = to_unsigned(10,COORD_WIDTH)) then
        run := '0';
      end if;
      if (odd = '1') then
        odd := '0';
        DVAL_IN <= '1';
        FVAL_IN <= '1';
        count := count + 1;
        CL_IN <= to_unsigned(8, LABEL_WIDTH);
        X_IN <= count;
        Y_IN <= count;
        wait for 200 ps;
      else
        odd := '1';
        DVAL_IN <= '0';
        FVAL_IN <= '1';
        --count := count + 1;
        CL_IN <= to_unsigned(0, LABEL_WIDTH);
        X_IN <= to_unsigned(333, COORD_WIDTH);
        Y_IN <= to_unsigned(333, COORD_WIDTH);
        wait for 200 ps;
      end if;
    end loop;
    
    
    DVAL_IN <= '0';
    FVAL_IN <= '0';
    CL_IN <= to_unsigned(8, LABEL_WIDTH);
    X_IN <= to_unsigned(222, COORD_WIDTH);
    Y_IN <= to_unsigned(222, COORD_WIDTH);
    run := '1';
    wait for 200 ps;
    
    while (run = '1') loop
      if (odd = '1') then
        odd := '0';
        DVAL_IN <= '1';
        FVAL_IN <= '1';
        count := count + 1;
        CL_IN <= to_unsigned(8, LABEL_WIDTH);
        X_IN <= count;
        Y_IN <= count;
        wait for 200 ps;
      else
        odd := '1';
        DVAL_IN <= '0';
        FVAL_IN <= '1';
        --count := count + 1;
        CL_IN <= to_unsigned(0, LABEL_WIDTH);
        X_IN <= to_unsigned(333, COORD_WIDTH);
        Y_IN <= to_unsigned(333, COORD_WIDTH);
        wait for 200 ps;
      end if;
    end loop;
    
    --wait;
  end process;
  
  M:  FlipBuffer port map (CLK, CL_IN, X_IN, Y_IN, DVAL_IN, FVAL_IN, CL_OUT, X_OUT, Y_OUT, DVAL_OUT, FVAL_OUT);
  
end bench;