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Hi,
i've realized an i_q demodulator for fsk message.
The frequencies for the 0 and for the 1 are spaced 400Hz; the baud rate is up 200baud. The frequencies are in the audio range (for example F0=4050Hz and F1=4450Hz).
That kind of demodulator needs two Low Pass filter for the i and q components.
The problem is that in order to obtain an attenuation > 3dB @ 200Hz and >40db @ 400Hz the order of filter implemented is too high (now it is 1000) and the used resources overcome the max allowable by my FPGA (i.e. Memory Bits > 400.000).
Is there any way or another kind of filter that could help me?
Any others ideas?
Thanks a lot....
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so your high frequency is 4450Hz yet your symbol rate is 200 symbols/sec(baud). I don't get it. what is your sampling rate?
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