FIFO (Dual port ram)

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can someone explain how the read and write address works in dual port ram for FIFO.

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Cliff Cummings has some nice papers on FIFOs (see the SNUG 2002 papers)

http://www.sunburst-design.com/papers/

I use the Altera scfifo and dcfifo. They work fine. There's really no reason not to use them. You can abstract them out of your 'working' design later.

Cheers,

Dave

I guess I will use the scfifo 1st.

Thank you!

Hello,

I am using the scfifo but I keep getting an error that makes no sense.

I am sending values (data) into the fifo and my w_enable<= 1.

But my usedw is always 1? and full is always 0.

My word length is 8 and the number of Bits =20.

My code might be a little bit confusing because I have the other variables that I wil use later once I understand how 1 fifo works.

I am trying to use 2 fifo and 3-shift register to for convolution pipeling. But the important part is the enable block

module conv_buffer3x3(CLK,reset,en,inPixel,fBuff,line_end,P1,P2,P3,P4,P5,P6,P7,P8,P9);
  
parameter nRows=8;
parameter nCols=8;
parameter kRows=3;
parameter kCols=3;
parameter INT_WIDTH=20;
parameter ADD_WIDTH= 5; //line is (k-1)*N +K;
parameter KxK=9;
parameter filled= 63; //line is (k-1)*N +K;
input CLK, reset,en,line_end;
input  inPixel;
output reg fBuff;
output reg  P1,P2,P3,P4,P5,P6,P7,P8,P9;
reg  fiforeg1_1,fiforeg1_2,fiforeg1_3;
reg  shiftreg1_1,shiftreg1_2,shiftreg1_3;
reg  shiftreg2_1,shiftreg2_2,shiftreg2_3;
reg  shiftreg3_1,shiftreg3_2,shiftreg3_3;
wire full_f1,full_f2;
wire  usedw_f1,usedw_f2;
wire  output_f1,output_f2;
reg re_f1,re_f2,we_f1,we_f2;
wire empty_f1,emptyF2;
reg  data_f1, data_f2;
reg  cnt;
always @(posedge CLK) begin //or negedge RST)
  if (en) begin
    cnt<=cnt+1;
    if (cnt>=0 && cnt<filled) begin
      fiforeg1_3<=inPixel;
      fiforeg1_2<=fiforeg1_3;
      fiforeg1_1<=fiforeg1_2;
      if (cnt>2) begin
        data_f1   <=fiforeg1_1;
        we_f1     <=1; 
        fBuff<=0; 
      end
    end
  end
  
  else  begin
    //shiftreg1_1<=0; shiftreg1_2<=0;shiftreg1_3<=0;
//    fiforeg1_1<=0; fiforeg1_2<=0; fiforeg1_3<=0;
cnt<=0;
we_f1<=0;
  end
end 
fifo_v1 FIFO1(CLK,data_f1,re_f1,we_f1,empty_f1,full_f1,output_f1,usedw_f1);
//fifo_v1 FIFO2(CLK,data_f2,re_f2,we_f2,empty,full_f2,output_f2,usedw_f2);
endmodule

Thank you

Look at your timing waveform. rdreq is red and its not assigned in the code.

You need to make sure that all signals on the FIFO are connected and driven to valid logic levels.

How about the FIFO reset signal? I don't see that being driven either.

Cheers,

Dave