Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorFIFO (Dual port ram)
Hello, I am trying to perform 3x3 kernel image convolution by using 2 FIFO and 3 shift registers so that I can implement a pipelined fifo I will prefer not to use the FIFO ip...
Altera_ForumHonored Contributor
Honored ContributorLook at your timing waveform. rdreq is red and its not assigned in the code.
You need to make sure that all signals on the FIFO are connected and driven to valid logic levels. How about the FIFO reset signal? I don't see that being driven either. Cheers, Dave
