Honored ContributorHello,
My PLL with feedback could simulated and synthesis for 400MHz; however, my Stratixiii only generated 200MHz instead of 400MHz. When I use SignalTap to probe the FBOUT, my synthesis failed with an error " FBOUT must drive a pin". I did connect FBOUT to a pin. Any suggestion?
Honored Contributor1 - Are you sure you provided an input clock of the same frequency as specified in the megawizard? I believe it defaults to 100MHz.
2 - What the error means is that FBOUT must "only" drive a pin. You can't Signaltap it because that adds an illegal connection to the signal. You wouldn't be able to see anything anyway unless you had an 800MHz clock to sample with. JakeHonored Contributor1) The PLL clock input is 400MHz. PLL clock output, FBIN in, and FBOUT are also 400MHz. From simulation, the PLL locked to this frequency.
2) Thank for the note on "cant SignalTap at FBOUT" and the maximum sampling rates. I think my external PLL filter might pulled down the FBIN.Honored ContributorJake,
I cannot set the PLL feedback to differential. Are there away to get around of these?Honored ContributorWhy can't you set it to differential?
Jake