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Altera_Forum's avatar
Altera_Forum
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17 years ago

FBOUT must drive a pin

Hello, My PLL with feedback could simulated and synthesis for 400MHz; however, my Stratixiii only generated 200MHz instead of 400MHz. When I use SignalTap to probe the FBOUT, my synthesis ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

1 - Are you sure you provided an input clock of the same frequency as specified in the megawizard? I believe it defaults to 100MHz.

2 - What the error means is that FBOUT must "only" drive a pin. You can't Signaltap it because that adds an illegal connection to the signal. You wouldn't be able to see anything anyway unless you had an 800MHz clock to sample with.

Jake