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Honored Contributor
Honored ContributorFBOUT must drive a pin
Hello, My PLL with feedback could simulated and synthesis for 400MHz; however, my Stratixiii only generated 200MHz instead of 400MHz. When I use SignalTap to probe the FBOUT, my synthesis ...
Altera_ForumHonored Contributor
Honored Contributor1) The PLL clock input is 400MHz. PLL clock output, FBIN in, and FBOUT are also 400MHz. From simulation, the PLL locked to this frequency.
2) Thank for the note on "cant SignalTap at FBOUT" and the maximum sampling rates. I think my external PLL filter might pulled down the FBIN.
