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Honored Contributor
Honored ContributorFan-out too weak to trigger SignalTap II ??
I set up two instances in signaltap, one instance contained a signal that would trigger acquisition at rising edge, the other instance contained the same signal but would be triggered by something el...
Altera_ForumHonored Contributor
Honored ContributorThank you zoomkrupesh. After setting up an additional PLL for signaltap with frequency that is twice as fast as the working frequency, I had a setup violation on a path from a node in my design to a node in signaltap module.
I'm not sure why there's clock domain crossing here since my understanding is that the second, faster clock is for signaltap sampling only and does not interfere the main module. Any suggestion?
