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MIT_R_D
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4 years ago

Facing Issue On Design Example: Intel Arria 10 FPGA Remote System Update via PCI Express*

Hi
I am trying to emulate the Design Example: Intel Arria 10 FPGA Remote System Update via PCI Express*. i am facing issue when we trying to download any application
can anyone help me on this?

Steps Followed by me
Step. 1 : Load Mater_Image jic file through onboard blaster - Success
Step 2: Reboot the dvk - Success - Four LED glows
Step 3: Copy driver, Install & run the driver - Success
Step 4: download application - Facing issue(PFA)

#######################################################################################
Flash Device ID: 1021bb20
Step1 : Do you want to download the application image to FLASH?
(Please input 'y' or 'n' to select, and press ENTER to go on):y
Step2 : Please input start and end address of application image downloaded to FLASH.
(You could get below information from *.map file, and input here.)
(Warning: Please use start address 0x0 if you are downloading factory image!!!)
START ADDRESS :0x04000000
END ADDRESS :0x5568FFF
Step3 : PLease input program file directory.
(For example: /home/rsu_over_pcie/user/ru_auto.rpd)
/home/jetson/GRL_C2V/A10_Flash/vel_image/app2c_auto.rpd
Info : Download application image into Flash, file size is 22450176 Bytes, start address is 0x4000000

Erasing EPCQ flash ...
################################################## 100%
Writing EPCQ flash ...
################################################## 100%
Reading back data from Flash ...

Warning : Flash data error at addr 0xc000000, expected data is 0x3a, but read data is 0x0
Warning : Checking stop due to read back data error
Step4 : Do you want to reconfig FPGA?
(Please input 'y' or 'n' to select, and press ENTER to go on):


Note: I am able perform Step4 (reconfig) With initial configuration(loaded using onboard blaster). Yes, able to reconfig different application

@Ryan_M_Intel

Thanks for the example design.

16 Replies

  • Hi,

    1. I noticed from all your previuos reply, all the details were tested using Page_4 address.

    Have you try to program Page_0 and Page 1? Are they success?

    Page_0 0x00000020 0x01569FFF (0x0156958B)

    Page_1 0x02000000 0x03568FFF (0x03568F27)

    Page_2 0x04000000 0x05568FFF (0x05568F27)

    2.On top of that, at step 4, did you press Y? If yes, did the FPGA able to boot up and work as intended?

    Step4 : Do you want to reconfig FPGA?

    (Please input 'y' or 'n' to select, and press ENTER to go on):

    Regards,

    Aiman


    • MIT_R_D's avatar
      MIT_R_D
      Icon for Occasional Contributor rankOccasional Contributor

      @NurAiman_M_Intel

      1. Have you try to program Page_0 and Page 1? Are they success?
      Yes, We try to program Page_0 and Page 1; its not success

      2.On top of that, at step 4, did you press Y? If yes, did the FPGA able to boot up and work as intended?
      No, When we program Page_0 or Page_1 or Page_2 through PCIe, FPGA did not boot up

  • Hi,


    Can you please try again by following below:


    [1] Erase the flash using Quartus Programmer.

    [2] Restart the flow by generating the JIC file with image 0, image 1 and image 2 in it and then program it into the flash.

    (Follow page 8 in the document)

    [3] generate the rpd file for image 2, then try again to update the image using terminal

    (follow page 18 - section 3.7.2)


    Regards,

    Aiman


  • We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.