Facing Issue On Design Example: Intel Arria 10 FPGA Remote System Update via PCI Express*

Hi,

Greetings!

1. When following the design example, is there any changes made in the design? If yes, which part?
   - No change on design example. We are used same master_image
2. Is the design already programmed? It seems like it has but error at readback. If so, is the design functioning as intended?

- Write flash is completed. Readback error
- when we perform step 4(Do you want to reconfig FPGA?) with proper start address. its showing " Users Watchdog Timer timeout"
- The design not functioning as intended

Step4 : Do you want to reconfig FPGA?
(Please input 'y' or 'n' to select, and press ENTER to go on):y
(Warning: Please use start address 0x0 if you are reconfiguring to factory image!!!)
START ADDRESS :0x04000000
Info : Saving PCI control registers of the board.
-- Write 32bits 0 to bar 0, addr 2020004
-- Write 32bits 0 to bar 0, addr 2020008
-- Write 32bits 1 to bar 0, addr 2020010
-- Write 32bits 4000000 to bar 0, addr 202000c
-- Write 32bits 1 to bar 0, addr 2020018
Info : Restoring PCI control registers of the board.
-- Read 32bits ffffffff from bar 0, addr 2020000
Info : Altera Remote Update: Users Watchdog Timer timeout