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SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
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F-tile Reference and System PLL Clocks: mising port documentation

Hello Intel forums, I'm exploring the settings of the "F-Tile Reference and System PLL Clocks Intel FPGA" IP. There is a setting "Refclk #X is active at and after device configuration" which is ena...
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  • Farabi_Altera's avatar
    Farabi_Altera
    1 year ago

    Hello,


    Q1- Can out_coreclk_i used to drive IOPLL?

    <ANS> No. out_coreclk_i is not routed through dedicated clock paths required by IOPLL.


    Q2- Is there workaround to indirectly use out_coreclk_i for IOPLL reference?

    <ANS> a. Use Clock Control IP.

    b. Use dedicated clk routing.


    Q3- Fitter error and HSSI_PLDADAPT_RX

    <ANS> error is due to placement constraints and routing limitation between HSSI components and core logic. In your case, HSSI_PLDADAPT_RX is constrained to a specific region, but the core logic needs to connect to is placed elsewhere, and there is no valid routing path. Please review your location constraints. Avoid using out_coreclk_i for clocking components that require dedicated routing.


    Q4- Can altera_fifo be driven by out_coreclk_i ?

    <ANS> yes, they are not dependent on IOPLL reference. FIFO IP is designed to work with fabric routing.


    regards,

    Farabi