--- Quote Start ---
It performs fine. I copied and pasted in my design the hdl code provided by Altera and it worked immediately, without any effort.
--- Quote End ---
Before that You had to program DS28E01 with secret code with the use of the same FPGA.
Can that be done several times?
How to check, that DS28E01 really got programmed?
In the "Cyclone III FPGA Design Security Solution Using SHA-1 with DS28E01 Reference Design User Guide" it is said, that "After the SHA-1 IFF module enables the user design, the block will be turned off to save power consumption."
What is the form of the "Enable" signal?
A constant high level even after the SHA-1 IFF module will be turned off or a pulse?
Honored Contributor
