Expressing Pipeline Delays in Verilog

I have been searching for an answer to this problem for awhile now, but have yet to find any information online that would help me. I hope this is the appropriate forum to ask a Verilog question. I'm using an Altera device, and it involves Quartus, so it's not completely irrelevant.

Suppose I need to calculate: "x + y / z". The width of the variables is a parameter called WIDTH. Obviously, y / z could be very expensive, so I build a pipelined divider module. The length of the pipeline is dependent on the WIDTH.

Now, the result of y / z comes out of the pipelined divider. Since it's pipelined, it is delayed, so I need to load x into a FIFO with the same length as the divider pipeline. Problem! The length of the divider pipeline is calculated in the divider. The parent module has no access to the parameters of the children (at least in QII). So the following would not work:

**** I omit a lot of code and structure here. Just trying to get the point across ****

module MY_FUNC(clk, x, y, z, result);
parameter WIDTH = 1; // default.
divider#  (.WIDTH(WIDTH)) div_blk (clk, y, z, divide_result);
FIFO#  (.WIDTH(WIDTH), .LENGTH(div_blk.PIPELINE_LENGTH)) fifo_blk (clk, x, delay_x);
always ...
result <= delay_x + divide_result
endmodule
module divider(...);
parameter WIDTH = 1; //default
parameter PIPELINE_LENGTH = WIDTH >> 1;
endmodule

The above code is what I first tried, but the synthesizer won't let me do div_blk.PIPELINE_LENGTH. I've tried a bunch of other ideas, but none of them solve the problem.

Is there a way to do this?

And yes, I know QII has a divider megafunction. This is just an example. My project has pipelines everywhere and it has gotten very difficult keeping track of their lengths.