Expressing Pipeline Delays in Verilog

I am not clear why the pipe length is not fixed to maximum worst case

Also consider converting division to multiplication. This requires a LUT and is convenient for small widths.

To convert x/z to multiplication:

pre-multiply z to suitable power of 2 then divide by truncation to get equivalent result:

e.g.:

1 * 1024/1 = 1024

2* 1024/2 = 1024

....

insert 1024, 1024/2 ... in LUT then

multiply LUT values by x and truncate off 10 bits.