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The length of the divider pipeline is calculated in the divider.
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It's not exactly clear what you mean here. I'm not aware of modules, that "decide" about pipeline delay at will. Normally the delay is set as a parameter by the user when instantiating the module. If the module's pipeline delay has to be choosen based on other parameters e.g. word length, they are known at the interface.
I understand, that you're asking for something like a module "output parameter", that reports the actual pipeline delay. I think it's not provided by Verilog or VHDL.
There may be a workaround, by using an output signal for this information. It turns into a constant value during compilation. If it's fed to a variable delay construct, the compiler possibly can utilize it to set the pipeline delay at compile time rather than actually implementing a variable delay.
But my preferred solution would be to gather all respective module parameters in a project global define file (Verilog) respectively a parameter package (VHDL).
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