I am looking for example designs or tutorials showing how to communicate two Altera boards using simple protocols. The purpose is to see how the two devices interact by transmitting data back and forth and to check the transmission somehow. I am using two Altera Transceiver Signal Integrity Development Kit, Stratix IV GT (EP4S100G2F40I1) boards. Please help to advice if anyone knows such tutorials and examples. Also, any suggestions are highly appreciated. Thanks.

--- Quote Start --- I am looking for example designs or tutorials showing how to communicate two Altera boards using simple protocols. The purpose is to see how the two devices interact by transmitting data back and forth and to check the transmission somehow. I am using two Altera Transceiver Signal Integrity Development Kit, Stratix IV GT (EP4S100G2F40I1) boards. Please help to advice if anyone knows such tutorials and examples. Also, any suggestions are highly appreciated. --- Quote End --- What are you looking to test? The transceivers? At what data rate? What have you tried so far, eg., do you know how to configure the ALTGX and ALGX_RECONFIG components? What do you have in addition to the GT boards? Do you have break out cables? A synthesizer to provide a common clock between the boards? Cheers, Dave

Many thanks to Dave and please find my answers as following: 1-What are you looking to test? The transceivers? Yes, the main purpose is to to test transceivers, in particular with the Altera PHY IP cores. But besides these, I want to know how to create a design for two boards to communicate one another using some simpler protocol than the PHY IP cores. The data rate can be any not greater than 11.3Gbps 2-What have you tried so far? I have tried to test XCVR with On-chip debugging design examples provided by Altera. Then I created similar designs with Lowlatency and Custom PHY for various data rates using Qsys. However, I would like to have a 10Gbase-r PHY design and I could not create this in Qsys. I don't know if it is possible to create such design by using available components in Qsys. 3-Do you know how to configure the ALTGX and ALGX_RECONFIG components? I have general idea about the ALTGX and ALTGX_RECONFIG but have not ever used these as I want to try designing with Qsys first. 4-What do you have in addition to the GT boards? Do you have break out cables? A synthesizer to provide a common clock between the boards? I have SMA cables for physical connection between the two boards. For a synthesizer to provide the common clock, if you can make this clearer? Thanks.

--- Quote Start --- 1-What are you looking to test? The transceivers? Yes, the main purpose is to to test transceivers, in particular with the Altera PHY IP cores. But besides these, I want to know how to create a design for two boards to communicate one another using some simpler protocol than the PHY IP cores. The data rate can be any not greater than 11.3Gbps --- Quote End --- Unfortunately, there are lots of protocols, and lots of reasons for selecting a specific one. What is your final application? Are you going to be having FPGAs communicating with FPGAs, or do you need to interface with a 10G switch, or a Serial RapidIO switch, or SATA drives, or ... etc etc? --- Quote Start --- 2-What have you tried so far? I have tried to test XCVR with On-chip debugging design examples provided by Altera. Then I created similar designs with Lowlatency and Custom PHY for various data rates using Qsys. However, I would like to have a 10Gbase-r PHY design and I could not create this in Qsys. I don't know if it is possible to create such design by using available components in Qsys. --- Quote End --- What have you managed to test? Have you only tried these in hardware, or have you simulated them in Modelsim? --- Quote Start --- 3-Do you know how to configure the ALTGX and ALGX_RECONFIG components? I have general idea about the ALTGX and ALTGX_RECONFIG but have not ever used these as I want to try designing with Qsys first. --- Quote End --- You're doing things in reverse. Qsys is a convenience for connecting components. For a successful system design, you need to understand how these components work. For that understanding, you should start by configuring an ALTGX, an ALTGX_RECONFIG, create a reset controller, and then get them working in simulation and hardware. Use SignalTap II to trace that the hardware does what the simulation does (it doesn't, but the handbook tells you the difference - the key is being able to see and understand the differences). Since all other components are based on these two components, this will give you a fundamental understanding of how the interfaces work. --- Quote Start --- 4-What do you have in addition to the GT boards? Do you have break out cables? A synthesizer to provide a common clock between the boards? I have SMA cables for physical connection between the two boards. For a synthesizer to provide the common clock, if you can make this clearer? --- Quote End --- If one board uses a 156.25MHz reference that is actually a few kHz high, and the other board uses a reference that is a few kHz low, then one board will send data to the other faster than ideal. The clock-and-data recovery (CDR) in the receiver will track the higher frequency, however, if you use a FIFO to cross clock domains between the recovered clock and the local clock, you will eventually get a FIFO overrun (or underrun in the case of a slower transmitter). Protocols like 10G take care of this by having protocol codes that can be added or deleted. If you are implementing FPGA-to-FPGA communications, then the system becomes simpler if you use a synchronous reference. You can implement this reference using an external synthesizer and send a copy of the signal to each board, or you can use one of your boards as the clock source and the other can receive a clock from the first, and use it for clocking its receiver logic. To understand what I am talking about, configure an ALTGX transmitter with one reference frequency (156.25MHz + something), and an ALTGX receiver with another frequency (156.25MHz - something), and simulate it using Modelsim. If you don't know how to use Modelsim, its time to learn :) Ask questions, and I'll try to help. Cheers, Dave

Thanks Dave very much for your time and very detailed explanation. Let me describe briefly my final application. I am going to build a 10Gbps Ethernet Passive Optical Network (EPON) system where one FPGA will play a role as a center office device (OLT) and several other FPGAs will be customer premises (ONU). The boards will interface SFP+ modules. The design will consist of a physical layer protocol (probably by using Altera 10GBASE-R IP core) and my own implementation of MAC protocol (probably by modifying Altera 10GbE MAC IP core). The MAC for OLT device is different from that for ONUs. Therefore, I am trying to have physical layer first. I studied the Altera XCVR PHY IP Core User Guide and XCVR Architecture in Stratix IV manual. Then I tested the provided On-chip XCVR debugging examples in harware (not yet in Modelsim). However, 10GBASE-R is provided by Altera without a similar example for testing in hardware, so I tried to create that in Qsys with Avalon ultilities. With some knowledge from reading specs and Qsys, I though/hoped that I would create a complete 10GBASE-R design, then simulate it in Modelsim as well as test it on harware. I hoped that this top-down approach would help me understand the overview of my design more quickly. Moreover, as the PHY layer is provided as IP core, I do not really want to spend much time for this. I just want to know how to test this in hardware and know how to interface this with the other components in my final design. The major part of my project is to design the customized MAC sublayer. That is why I am doing things in reverse. I don't know if I am right when choosing this approach. Please give me some advice or/and suggest me better way(s) to reach my target application. For sure, to have a better understanding, I will learn to designs by configuring the ALTGX, RECONFIG,...like you recommended and learn to simulate in Modelsim. Also, I will learn to work with the SignalTap II and synthesizer soon. Again, thank you very much and look forward to your further advice.

--- Quote Start --- I am going to build a 10Gbps Ethernet Passive Optical Network (EPON) system where one FPGA will play a role as a center office device (OLT) and several other FPGAs will be customer premises (ONU). The boards will interface SFP+ modules. The design will consist of a physical layer protocol (probably by using Altera 10GBASE-R IP core) and my own implementation of MAC protocol (probably by modifying Altera 10GbE MAC IP core). The MAC for OLT device is different from that for ONUs. --- Quote End --- Ok, thanks for the description. --- Quote Start --- Therefore, I am trying to have physical layer first. I studied the Altera XCVR PHY IP Core User Guide and XCVR Architecture in Stratix IV manual. Then I tested the provided On-chip XCVR debugging examples in harware (not yet in Modelsim). However, 10GBASE-R is provided by Altera without a similar example for testing in hardware, so I tried to create that in Qsys with Avalon ultilities. With some knowledge from reading specs and Qsys, I though/hoped that I would create a complete 10GBASE-R design, then simulate it in Modelsim as well as test it on harware. --- Quote End --- My recommendation would be to take the XCVR debug example, which works, and simulate it. That'll allow you to probe a working design. I assume this is the 10GBASE-R IP you are looking at: http://www.altera.com/products/ip/iup/ethernet/m-alt-10gbase-r-pcs.html Note that 64/66B encoding is not supported in the Stratix IV hard-IP PCS, so it gets implemented in the fabric. You should synthesize to see how much logic the PCS layer is using. Given that the Stratix IV GT might not be a good use of resources, have you considered using a GX device with an external PHY? --- Quote Start --- I hoped that this top-down approach would help me understand the overview of my design more quickly. --- Quote End --- It might, if you also know how to simulate Qsys and create custom components. However, if you're introducing lots of new concepts, then you might actually be making the design more complicated. --- Quote Start --- Moreover, as the PHY layer is provided as IP core, I do not really want to spend much time for this. I just want to know how to test this in hardware and know how to interface this with the other components in my final design. The major part of my project is to design the customized MAC sublayer. That is why I am doing things in reverse. --- Quote End --- What you really should be doing then is getting the PHY working in the simulator so that you can simulate while working on your custom logic. Cheers, Dave

Example designs for communicating two Altera boards

49 Replies

Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
If the board has two transmitters and two receivers on the SMA connectors, then you could use two SMA-to-SPF+ adapters. You could then connect two SFP+ cables to a desktop 10Gbps SFP+ card or to two ports on a 10Gbps switch. That way you can have 10Gbps continuous through the link.
--- Quote End ---

Does this mean instead of using normal Ethernet interface to transfer data from host PC, device/board receive data from host PC via SMA connectors. And to do so, the host PC must be equipped with a 10Gbps SFP+ card? If so, how to realize this transmission? Any tutorial related to this?

Thank you.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Does this mean instead of using normal Ethernet interface to transfer data from host PC, device/board receive data from host PC via SMA connectors. And to do so, the host PC must be equipped with a 10Gbps SFP+ card? If so, how to realize this transmission? Any tutorial related to this?

--- Quote End ---
Not quite. Here's what I would try to find;

1) A PCIe 10Gbps NIC (network interface card) with SFP+ connectors. Eg., Newegg has them

http://www.newegg.com/product/product.aspx?item=n82e16833106057
http://www.newegg.com/product/product.aspx?item=n82e16833120384

2) A couple of SFP+ to SMA breakout cables or boards, eg.,

http://hitechglobal.com/boards/modules/sma_to_sfp+.htm

3) Plug the NIC into your test PC, plug the SFP+ cable into the NIC and the adapter board, and then wire the SMAs onto your SI kit. You can also use the adapter boards to connect your kits together.

However, in hindsight, you should have just purchased a GT board with SFP+ connectors on it already, eg.,

http://www.hitechglobal.com/boards/stratix4gx.htm

Note that if you are just connecting your two SI kits together using 10Gbps, you can just use SMA cables there.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
It looks like your script output stops right around the time Java is started. Perhaps Java on Windows Server 2008 is broken.
--- Quote End ---

I have just tried the generation with Quartus II 11.0 sp1 installed in Window 7 OS. And it was fine. So, I will check the time java on the server. In case, it does not help, we will need to reinstall an supported OS.

Now I see why my boss want me to use the Windows Server 2008. The server has a NIC with SFP+ connectors and he has been told that the NIC just works with Win Server 2008. I need to investigate this soon. But, if this is true, how should we do?

--- Quote Start ---
You will not get any response to requests for support until you are using a supported OS.
--- Quote End ---

A reason strong enough for us to decide changing the OS.

Thank you very much.
PLMT
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

Now I see why my boss want me to use the Windows Server 2008. The server has a NIC with SFP+ connectors and he has been told that the NIC just works with Win Server 2008. I need to investigate this soon. But, if this is true, how should we do?

--- Quote End ---

Look at the $600 Intel NIC. Check if its supported under Windows 7 and Linux RedHat 6 (or Centos 6). Even if you're not going to use Linux, its a good indicator that the NIC works well and is documented (since the Linux guys had enough info to write a driver).

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Dear Dave,

Thank you very much, your explanation and instruction help me understand my target system really better. Still, I have some doubts as follow.

--- Quote Start ---
1) A PCIe 10Gbps NIC (network interface card) with SFP+ connectors. Eg., Newegg has them

http://www.newegg.com/product/product.aspx?item=n82e16833106057
http://www.newegg.com/product/product.aspx?item=n82e16833120384
--- Quote End ---

My boss said that we have NIC with SFP+ connector for our server. So I assume that we have already had this by now.

--- Quote Start ---
2) A couple of SFP+ to SMA breakout cables or boards, eg.,
http://hitechglobal.com/boards/modules/sma_to_sfp+.htm
--- Quote End ---

And this is what we will need to have to realize our target application, am I right?

--- Quote Start ---

3) Plug the NIC into your test PC, plug the SFP+ cable into the NIC and the adapter board, and then wire the SMAs onto your SI kit.
--- Quote End ---

This is how I set up a connection from a test PC to my SIV GT SI board for transferring 10Gbps, is that right?

My next wonder is how I can transfer data from the test PC to board in terms of implementation? if there is an existing tool for this or I need to create my own software/design?

--- Quote Start ---
However, in hindsight, you should have just purchased a GT board with SFP+ connectors on it already, eg.,
http://www.hitechglobal.com/boards/stratix4gx.htm
--- Quote End ---

I am not sure if I understood your point here. But I still do not have SFP+ connector. I have only the XCVR SI Dev kit, SIV GT, eg.,
http://www.altera.com/products/devkits/altera/kit-stratix-iv-gt-si.html

--- Quote Start ---
Note that if you are just connecting your two SI kits together using 10Gbps, you can just use SMA cables there.

--- Quote End ---

This is clear for me. This is what I am doing for testing the XCVR Toolkit examples.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Look at the $600 Intel NIC. Check if its supported under Windows 7 and Linux RedHat 6 (or Centos 6). Even if you're not going to use Linux, its a good indicator that the NIC works well and is documented (since the Linux guys had enough info to write a driver).

--- Quote End ---

It says "Support for most Network Operating Systems". So I think that no way to have a driver in Windows 7 or XP. You have any ideas?
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
It says "Support for most Network Operating Systems". So I think that no way to have a driver in Windows 7 or XP. You have any ideas?
--- Quote End ---

Read the datasheet:

http://www.intel.com/content/dam/doc/product-brief/10-gigabit-af-da-dual-port-server-adapter-brief.pdf

I suspect it would work under Windows 7. You could always contact Intel and ask, or use Google.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

My boss said that we have NIC with SFP+ connector for our server. So I assume that we have already had this by now.

--- Quote End ---

But you also said your boss thought it would only work under Windows Server 2008. If that is the case, then just buy a new NIC that is compatible with the OS that is also compatible with Quartus.

--- Quote Start ---

My next wonder is how I can transfer data from the test PC to board in terms of implementation? if there is an existing tool for this or I need to create my own software/design?

--- Quote End ---

Its called network or sockets programming.

--- Quote Start ---

I am not sure if I understood your point here.

--- Quote End ---

The point was that you purchased a really expensive board before figuring out what you really want to do, and now you find that you have to purchase other really expensive adapters to add the missing functionality. The lesson to take from this is; design first, and then buy.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

I suspect it would work under Windows 7. You could always contact Intel and ask, or use Google.

--- Quote End ---

Yeah, thanks a lot. I just saw Wins Vista is supported so maybe Wins 7 is also supported. I will check this soon.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Its called network or sockets programming.

--- Quote End ---

This absolutely answers my wonder.

--- Quote Start ---
The point was that you purchased a really expensive board before figuring out what you really want to do, and now you find that you have to purchase other really expensive adapters to add the missing functionality. The lesson to take from this is; design first, and then buy.
--- Quote End ---

Thanks for pointing out our lesson. Actually, even before I realize this uneconomic issue thanks to your explanation, I was feeling that our choice of device was not well decided as it is not easy to find reference designs, examples, tutorials provided for our device. So it takes more time from me.

Again, thank you very much Dave, I have learnt a lot. If possible, I will be back to bother you when I have further wonders.

Best,
PLMT

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Example designs for communicating two Altera boards

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