evb cyclon v soc kit ddr3 throughput measurement is low

hi Adzim,

thank you for answering.

here are the settings for the ddr ip:

 also, the board settings and memory timing are according to the evb cyclone v soc development kit.

the memory device is: mt41k256m16ha-125 x2 .

there were no timing issues regards to the ddr.

more details about the design:

we have 2 fifo's -one in the write side.and one on the read side.

we are writing with data counter that increments with clock of 78.125mhz(10gbps).

we are reading from the fifo on the write side in 200mhz (avalon bus).

we are reading from the fifo on the read side in 5gbps(can be change).

hope this is helpful,

just a reminder: in simulation everything works fine.

when we try to test it on board it does not .

BR,

Ram.