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ramsoffer_123's avatar
ramsoffer_123
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

evb cyclon v soc kit ddr3 throughput measurement is low

hi everyone, Im trying to read and write to ddr3 on the EVB cyclone v board. im using the ddr controller. i created read and write components to the controller through the avalon bus: ...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Ram,


I need further information from your IP setting in order to debug in this case.

Can you provide the DDR IP setting together with the memory device datasheet?


There are some points that I can share with you at the moment to improve the performance.

  1. Try to increase the burst length if possible.
  2. Perform the read and write transaction in sequence. For example, perform all write transaction first and then read.


You can set the arbiter from Platform Designer to identify the first priority module.


Is there any timing issue in the design?


Regards,

Adzim