Estimation IIR filter resources

Sounds like you haven't built your design yet. Here's some statistics for you: A 1998 tap FIR filter, applied to 24-bit input samples, using 24-bit taps, will (roughly) require four multiplies, 12 altsyncram's, 206 dff's, and 2148 lcell's and some I/O buffers. This is based upon a quick Yosys run.

A quick check of my favorite FIR generation script suggests that a 21 tap FIR, quantized to 24 bits, will meet your criteria with a (rough) 130dB stop band. Overdesigned? Perhaps.

What's missing in this discussion are such components as you might need to get your ADC input, to drive a DAC on the back end, and any components you might need to debug your design.

Somehow I don't think the filter you just described will be the limiting factor in your design.

Dan

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Hi,

In my application I will need implement high order (4), IIR, Butterworth, Low Pass filter, with cutoff frequency (-3dB) of ~1Hz and stop band of ~10Hz, with attenuation of -80dB. The input signal is sampled at rate of ~50ksps (32bits/sample).

The problem is that I need to select the right FPGA (Cyclone V) according to the filter resources. I haven't purchase yet the DSP builder (It takes time…) and the Simulink HDL coder but I can't delay the FPGA selection (will implemented on a costume board).

How can I estimate the resources to the IIR filter on those circumstances? I tried thought MATLAB filter editor and even managed to create some kind of VHDL code but I don’t have the relationship to ALTERA hardware (the "FPGA automation" tab is shut).

Thanks a lot,

Idan

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If you run @ 100MHz clock then you can use a MAC approach of one mult + accum for 2000 taps FIR. This is nothing in terms of resource except for large memory.

I have seen your case before and I suggested use any filter to your filtering requirement rather than specifically butterworth. For 50KHz input you can use FIR rather than think of IIR.

In fact it seems your best platform would be software dsp rather than fpga

I wonder why people are answering about FIR although the original post is asking for IIR. It should be also clear that a 2k taps FIR can't achieve the required fs/fc ratio, see previous thread http://www.alteraforum.com/forum/showthread.php?t=57301

80 dB stop band attenuation at 10*fc refers to a 4th order butterworth filter, two cascaded 2nd order blocks. As already mentioned in your previous thread, you need 27 extra fractional bits, refers to about 60 bit register width for 32 bit precision. A well considered design can process both 2nd order blocks sequentially using RAM based registers and coefficients. That's particularly interesting if you want to implement multiple filters.

A test compile of a similar filter with parameters adjusted to your requirements uses 40 of 46 available DSP blocks of an EP4CE10, a few registers, about 1k LEs and some RAM.

As also previously mentioned, the resource utilization can be reduced by switching to a modified implementation of the second order block, using two first order filters and an additional feedback.

@FvM,

Thank you, and good catch. I had thought the stopband cutoff was 10kHz, not 10Hz, and so my numbers were all off. You could still do this with a nice polyphase technique and probably less than 8 multiplies or so, but that would be a more difficult filter for a beginner to build.

Dan

A cutoff f 1/50k is possible with large fir or small iir but a transition band of -80dB at 10/50000 is just not realistic for fir or iir.

This requirement is too drastic for such a slow system. The likely best solution is multi stage decimation as suggested by FvM at some point in a previous related thread.

I will keep the band 1 ~ 10 Hz at 0dB (passband) during decimation then at the end say reaching Fs of 1000 (instead of 50000) will start final chop sharp at 1Hz down to 10Hz using Butterworth for the sake of the thread.

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A cutoff f 1/50k is possible with large fir or small iir but a transition band of -80dB at 10/50000 is just not realistic for fir or iir.

This requirement is too drastic for such a slow system.

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It's unhandy but feasible. There can be reasons why you want to operate a filter with this specification at 50 kS/s sampling rate. But it can be expected that a multi-rate design results in overall lower resource utilization.