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Hi,
In my application I will need implement high order (4), IIR, Butterworth, Low Pass filter, with cutoff frequency (-3dB) of ~1Hz and stop band of ~10Hz, with attenuation of -80dB. The input signal is sampled at rate of ~50ksps (32bits/sample).
The problem is that I need to select the right FPGA (Cyclone V) according to the filter resources. I haven't purchase yet the DSP builder (It takes time…) and the Simulink HDL coder but I can't delay the FPGA selection (will implemented on a costume board).
How can I estimate the resources to the IIR filter on those circumstances? I tried thought MATLAB filter editor and even managed to create some kind of VHDL code but I don’t have the relationship to ALTERA hardware (the "FPGA automation" tab is shut).
Thanks a lot,
Idan
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If you run @ 100MHz clock then you can use a MAC approach of one mult + accum for 2000 taps FIR. This is nothing in terms of resource except for large memory.
I have seen your case before and I suggested use any filter to your filtering requirement rather than specifically butterworth. For 50KHz input you can use FIR rather than think of IIR.
In fact it seems your best platform would be software dsp rather than fpga
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