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Altera_Forum's avatar
Altera_Forum
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17 years ago

errors in quartus when simulation

I have some code about LEDs cycle. I wrote two process, one is a time divider, the other is LED turn on according with divider. the project was complied, but quartus has some errors when staring simulation.

the error message is Error: Zero-time oscillation in node "|led_glimpse|lpm_mux:Mux4|mux_hfc:auto_generated|_~7" at time 5243903.5 ns. Check the design or vector source file for combinational loop.

I don't know where is wrong in the code to bring this error? Thanks!

the code is displayed as below:

process(Reset,clk)

begin

if Reset='0' then

counter<=(others=>'0');

elsif clk'event and clk='1' then

counter<=counter+1;

end if;

end process;

process(Reset,counter(10),datan)

begin

if Reset='0' then

ledn<=(others=>'0');

datan<=(others=>'0');

elsif counter(10)='1' then

datan<=datan+1;

case datan is

when "000" => ledn<="10000000";

when "001" => ledn<="00000001";

when "010" => ledn<="00000010";

when "011" => ledn<="00000100";

when "100" => ledn<="00001000";

when "101" => ledn<="00010000";

when "110" => ledn<="00100000";

when "111" => ledn<="01000000";

end case;

end if;

end process;

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    you can, but you're liable to have timing failures and have race conditions all over and all sorts of problems.

    What you need to do in your first process is wrap it up as a D-type flip flop process - just put

    if rising_edge(clk) then

    (or you can use:

    if clk'event and clk = '1' then

    at the top, then you wont have a problem. You can remove all signals other than the clock from the sensitivity list. What you have done by putting "if clk = '1' then" at the top is use the clock as a logic signal, not a clock, which is bad, and wont solve any problems.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    you can, but you're liable to have timing failures and have race conditions all over and all sorts of problems.

    What you need to do in your first process is wrap it up as a D-type flip flop process - just put

    if rising_edge(clk) then

    (or you can use:

    if clk'event and clk = '1' then

    at the top, then you wont have a problem. You can remove all signals other than the clock from the sensitivity list. What you have done by putting "if clk = '1' then" at the top is use the clock as a logic signal, not a clock, which is bad, and wont solve any problems.

    --- Quote End ---

    tnx a lot.