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you can, but you're liable to have timing failures and have race conditions all over and all sorts of problems.
What you need to do in your first process is wrap it up as a D-type flip flop process - just put
if rising_edge(clk) then
(or you can use:
if clk'event and clk = '1' then
at the top, then you wont have a problem. You can remove all signals other than the clock from the sensitivity list. What you have done by putting "if clk = '1' then" at the top is use the clock as a logic signal, not a clock, which is bad, and wont solve any problems.
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tnx a lot.
Honored Contributor
