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tomachie's avatar
tomachie
Icon for New Contributor rankNew Contributor
15 days ago

Errors in Agilex A3 A3CZ025BB18A BSDL

Hello,

I'm using Intellitech free BSDL compiler, and it gives an error because the PIN_BEHAVIOR for 1149.6 pins are not described.   This makes it unclear what pins have IEEE 1149.6 capability and its a syntax error. 

These are version 1.0 from 2025.  It may be good to check them before distribution.

Regards,
Tom.

 

attribute AIO_Pin_Behavior of Agilex_A3CZ025BB18A: entity is

-- *****************************************************************************************

-- * DESIGN WARNING *

-- *****************************************************************************************

attribute DESIGN_WARNING of Agilex_A3CZ025BB18A: entity is

 

iBSDL - Intellitech BSDL Compiler Version 14.25

Copyright (C) 1993-2026 Intellitech Corp. All rights reserved.

Line:1667

ERROR: Line:1668 attribute DESIGN_WARNING of Agilex_A3CZ025BB18A: entity is

^

Line:1669 "This Agilex_A3CZ025BB18ABSDL file supports 1149.1 and 1149.6"&

 

Missing QUOTE '"' or CONCATENATE '&' character in a QUOTED_STRING.

This type of error can be hard for the compiler to point to the correct line number.

 

ERROR: Check that all the ATTRIBUTES are in the correct order. BSDL has a strict order and a common error

is that the attributes are not in the correct order

See B.8.11

 

ERROR: Illegal structure to the BSDL. See B.8.1.1 Syntax

The order is fixed per B.8.1.1 as follows:

<BSDL description>::=

entity <component name> is

<generic parameter> (see B.8.2)

<logical port description> (see B.8.3)

<standard use statement> (see B.8.4)

{<use statement>} (see B.8.5)

<component conformance statement> (see B.8.6)

<device package pin mappings> (see B.8.7)

[<grouped port identification>] (see B.8.8)

<scan port identification> (see B.8.9)

[<compliance enable description>] (see B.8.10)

<instruction register description> (see B.8.11)

[<optional register description>] (see B.8.12)

[<register access description>] (see B.8.13)

<boundary-scan register description> (see B.8.14)

[<runbist description>] (see B.8.15)

[<intest description>] (see B.8.16)

{<BSDL extensions>} (see B.8.17)

[<design warning>] (see B.8.18)

end <component name>;

 

Programmable Logic Device
quality|reliability

2 Replies

  • tomachie's avatar
    tomachie
    Icon for New Contributor rankNew Contributor
    15 days ago

    from Tomachie.com report generation, it found problems even after fixing the BSDL manually.

    14.8 Boundary Scan Testability

    14.8.1 BSDL Identification

    One or more devices use an older IEEE 1149.1-2001 BSDL model which lacks descriptions needed for robust analysis. To get a Tomachie check mark, consider requesting an updated IEEE 1149.1-2013 BSDL from the IC supplier.

    Pin counts in the BSDL File(s) column show (BSDL pins matched / total BSDL pins). A BSDL with fewer pins than the schematic component is normal for multi-TAP devices where each BSDL describes one TAP.

    BSDL Device Matching
    RefDesPart NumberTAPsBSDL File(s)StdAC Std.Status
    U200A3CZ025BB18AI7S1A3CZ025BB18A.bsdl (209/209)2001     XNeeds attention
    The BSDL for A3CZ025BB18AI7S has a compliance error in that it has 1149.6 instructions (EXTEST_PULSE, EXTEST_TRAIN) but no cells or pins which actually support 1149.6 AC Coupled tests.

    14.8.2 Device IDs

    DEVICE ID from BSDL
    RefDesPart NumberVersionPart Number (ID)Manufacturer
    U200A3CZ025BB18AI7S0000001101100101100000001101110
    • FakhrulA_altera's avatar
      FakhrulA_altera
      Icon for Regular Contributor rankRegular Contributor
      11 days ago

      Hi Tom,

      For Agilex 3 devices, IEEE 1149.6 support is intended for HSSI transceiver-related pins. For the B18A package, transceivers are not supported, so this device/package is not expected to have applicable 1149.6 AC test pins.

      Try refer the following:
      (https://docs.altera.com/r/docs/849318/current/jtag-boundary-scan-testing-user-guide-agilextm-3-fpgas-and-socs/ieee-std.-1149.6-boundary-scan-register)(https://docs.altera.com/r/docs/848793/current/device-migration-guidelines-agilextm-3-fpgas-and-socs-c-series/package-b18a)
       

      Based on your report, the published BSDL file appears to maybe need internal review, both for the DESIGN_WARNING parse issue and for the inclusion of 1149.6-related content that does not appear applicable to this package.


      Please use the latest BSDL file from the Altera website for now. We will raise this for internal review.

      Regards,
      Fakhrul