Error:I/O std LVDS on output I/O pin cannot have Termination logic option setting

Hi,

Also if possible attach the project?

or Save the message/error and attach.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

--- Quote Start ---

Hi,

Also if possible attach the project?

or Save the message/error and attach.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

--- Quote End ---

I am unable to upload the project. So please check my attachment. In Schematic design, total output pins are 4. But in Pin planner output ports are missing only clk and reset pin is available

--- Quote Start ---

I don't see any output pins on your schematic design

--- Quote End ---

I am new to Altera Quartus. Doing LVDS testing from Altera Cyclone to Xilinx Board. Can anyone conform whether my block design is right or wrong. Design Flow sending input from 4-bit counter to single-ended input and differential output Alter buffer. Then passing differential output LVDS signal from Cyclone V board to Xilinx Custom Board. I tried lot but it is not working. So, anyone please guide me.