Error:I/O std LVDS on output I/O pin cannot have Termination logic option setting

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I don't see any output pins on your schematic design

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I am new to Altera Quartus. Doing LVDS testing from Altera Cyclone to Xilinx Board. Can anyone conform whether my block design is right or wrong. Design Flow sending input from 4-bit counter to single-ended input and differential output Alter buffer. Then passing differential output LVDS signal from Cyclone V board to Xilinx Custom Board. I tried lot but it is not working. So, anyone please guide me.