Error "not declared" but defined with `define?

Hello, I would very much appreciate some help with this puzzling error.

(Just to be clear, I know this simple example here won't produce anything useful. Its just to illustrate my problem. Thanks)

error (10161): verilog hdl error at def.v(12): object "high" is not declared

This is the code in def.v:

`define HIGH 1'h1
`define LOW 1'h0
module def (clk, q);
    input clk;
    output q;
    wire clk;
    reg q;
always @ (posedge clk)
begin
    q <=# 1 HIGH;
end
endmodule

Thanks!