error in simulation

Hi technovlsi,

First this is my code not yours but you are welcome to use it.

Is it simulation or synthesis that you produces error. Do use this module only or as part of larger project.

@kaz sir,

veryy sorry to declare this as my code,actuly sir,i got a big help from this forum.evryday browsing different peoples' problem,and solution given by u guys,are really helpful to a biggener of vhdl like me. however coming in the point,during simulation [sorry previously i told in synthesis] in the report window it tells that metavalue detected,turned to null.and gives null output,whatever value i have given. plz help.:oops:

Hi technovlsi,

You need to post more info. in fact you need to tell us about your testbench and how you are inputting into the LUT module. The LUT module itself has all its values defined right from reset. So it is likely your observation is wrong or the way you use the LUT.

@kaz sir,in testbench,

<reset : in std_logic;

clk : in std_logic;

clk_en : in std_logic;

theta : in std_logic_vector(11 downto 0);>

I GIVE RESET,CLK.CLK_EN ALL ARE 1,AND THETA = 60.GET NULL OUTPUT.

-------- I CAN;T UNDERSTAND ABOUT UR "LUT" SUGGESION SIR.CAN U PLZ EXPLAIN?

clock should be toggled to get edge regularly (ofcourse)

reset should be 1 initially then released to 0 otherwise you have to wait for ever.

hey !!

i´m wondering if anybody can tell me where i can find a tutorial, pdf, whatever for simulationg the whole fpga project (sopc system with nios II processor and nios II software, memories, several avalon slaves, vhdl blocks written by my self) in modelsim ?

thanks for your help !!! (http://dict.leo.org/ende?lp=ende&p=ci4ho3kmaa&search=tutorial&trestr=0x8001)