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Altera_Forum
Honored Contributor
14 years ago@kaz sir,in testbench,
<reset : in std_logic; clk : in std_logic; clk_en : in std_logic; theta : in std_logic_vector(11 downto 0);> I GIVE RESET,CLK.CLK_EN ALL ARE 1,AND THETA = 60.GET NULL OUTPUT. -------- I CAN;T UNDERSTAND ABOUT UR "LUT" SUGGESION SIR.CAN U PLZ EXPLAIN?